High Level Assembler - Opcodes overview

The table below lists all documented opcodes for IBM mainframe processors. Each opcode links to a text section with some additional info on the pertinent opcode.

Special thanks:
to David Bond for his instruction lists and tables.
And also to Jan Jaeger for his list of instructions not listed in IBM's Principles of Operation.

Opcode Assignments.

Remark:
Please note that the creation of descriptions for all individual instructions is an ongoing process. As yet these descriptions have been created only for opcodes X'00' through X'0F'. The other opcode descriptions are to follow later.

Base Set

Entries with a slightly darker background are no longer supported on current mainframe hardware and/or not supported by IBM's current version of HLASM. The associated mnemonics are printed in italics.
Opcodes that have no (known) mnemonic assigned to them are denoted by their hexadecimal opcode; these are explained below the table.
Extension sets have no associated mnemonic. These are denoted by their opcode in hexadecimal notation. These link to additional opcode tables.

Please note that instructions X'00' thru X'3F' are register-only operations. Adding X'40' generally yields the opcode of the associated register-and-storage instruction.

	_0	_1	_2	_3	_4	_5	_6	_7	_8	_9	_A	_B	_C	_D	_E	_F
0_	X'00'	X'01xx' XOPC			SPM	BALR	BCTR	BCR X'07m'	SSK	ISK	SVC	BSM	BASSM	BASR	MVCL	CLCL
1_	LPR	LNR	LTR	LCR	NR	CLR	OR	XR	LR	CR	AR	SR	MR	DR	ALR	SLR
2_	LPDR	LNDR	LTDR	LCDR	HDR	LDXR LRDR	MXR	MXDR	LDR	CDR	ADR	SDR	MDR	DDR	AWR	SWR
3_	LPER	LNER	LTER	LCER	HER	LEDR LRER	AXR	SXR	LER	CER	AER	SER	MDER MER	DER	AUR	SUR
4_	STH	LA	STC	IC	EX	BAL	BCT	BC X'47m'	LH	CH	AH	SH	MH	BAS	CVD	CVB
5_	ST	LAE	XDECO	XDECI	N	CL	O	X	L	C	A	S	M	D	AL	SL
6_	STD	XHEXI	XHEXO					MXD	LD	CD	AD	SD	MD	DD	AW	SW
7_	STE	MS							LE	CE	AE	SE	MDE ME	DE	AU	SU
8_	SSM	TRCD	LPSW	X'83' DIAG	BRXH JXH WRD	BRXLE JXLE RDD	BXH	BXLE	SRL	SLL	SRA	SLA	SRDL	SLDL	SRDA	SLDA
9_	STM	TM	MVI	TS	NI	CLI	OI	XI	LM	TRACE	LAM	STAM	SIO X'9C0x'	TIO X'9D0x'	HIO X'9E0x'	TCH X'9F0x'
A_	LMP				X'A4xx'	X'A5x' X'A5xx'	X'A6xx'	X'A7x'	MVCLE	CLCLE			STNSM	STOSM	SIGP	MC
B_	CTP STMC	LRA	X'B2xx'	X'B3xx'	IPB	SPB	STCTL	LCTL	LFI LMC	X'B9xx'	CS	CDS		CLM	STCM	ICM
C_	X'C0x'		X'C2x'		X'C4x'		X'C6x'		X'C8x'
D_	TRTR	MVN	MVC	MVZ	NC	CLC	OC	XC	RSP	MVCK	MVCP	MVCS	TR	TRT	ED	EDMK
E_	X'E00x'	PKU XDUMP	UNPKU	X'E3xx'	X'E4xx'	X'E5xx'	X'E6xx'	X'E7xx'	MVCIN	PKA	UNPKA X'EAxx'	X'EBxx'	X'ECxx'	X'EDxx'	PLO X'EExx'	LMD
F_	SRP	MVO	PACK	UNPK					ZAP	CP	AP	SP	MP	DP

X'00' = Abend S0C1
X'83' = Diagnose

Other Instructions

Some instructions do not fit in the tables because their opcodes are currently unknown. Specifically this is the case for the instructions below. These are all either Coupling Facility (CF) instructions, or MicroCode (MC) instructions. We do know a few opcodes that have been assigned to Coupling Facility instructions, but we have not been able to link any of these to one of the instructions below.

For PXLO we know of various subfunctions, what we know has been included in the table. SYSOP, too, appears to support subfunctions, unfortunatly, we have not been able to locate any details at all.

The empty slots indicate instructions that we have been able to associate with an opcode after all.

Facility	Operation description	Facility	Operation description	Facility	Opcode	Operation description	Facility	PXLO subfunction
CF		MC	Read Special Register	MC	BRFLG	BRanch on FLaGs	MC	Load Address Space Control Element
CF	test vector entry	MC	Write Special Register	MC	BRS	Branch Relative Special	MC	Load Absolute Address
CF	set vector entry	MC	AND Special Register	MC	EXGRI	EXtract program General Register Indirect	MC	Load Real Address
CF	test vector summary	MC	OR Special Register	MC	EXINT	EXtract INTerrupt	MC	Load Host Real Address
CF		MC	AND Logical Immediate	MC	MCEND	MilliCode END	MC	Load Page Table Entry
CF	send message	MC	OR Logical Immediate	MC	PXLO	Perform trans(X)Lator Operation	MC	Load Host Page Table Entry
CF	test message	MC	Insert Immediate Special Register	MC	RIRPT	Reset InterRuPTion	MC	Purge TLB
CF	Prepare Channel Buffer	MC	EXtract program General Register	MC	SPGRI	Set Program General Register Indirect	MC	Invalidate Page Table Entry
CF	Signal Channel buffer	MC	Set Program General Register	MC	SYSOP	SYStem OPeration	MC	Read TLB
CF	Test Channel Buffer	MC	EXtract program Access Register				MC	Write TLB
CF	Move Channel Buffer Data	MC	EXtract program Access Register Indirect				MC	Purge Data Cache
CF	Locate Channel Buffer	MC	Set Program Access Register				MC	Purge Instruction Cache
CF	Transfer Structure	MC	Set Program Access Register Indirect

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To the Base Set instructions.
To the Other Instructions.

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